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TC9WMA2FK
TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic
TC9WMA2FK
2,048-Bit (256 x 8 Bit) Serial E2PROM
The TC9WMA2FK is electrically erasable/programmable nonvolatile memory (E2PROM).
Features
* * * * * * * * * Serial data input/output Programmable in units of one word and collectively erasable in one operation Automatically set programming time (built-in timer) Programming time: 10 ms (max) (VCC = 3.0 to 5.5 V) 12 ms (max) (VCC = 2.3 to 2.7 V) Overwrite enabled or disabled by software Single power supply and low power consumption Operating voltage range for reading: VCC = 1.8 to 5.5 V Operating voltage range for writing: VCC = 2.3 to 5.5 V Wide operating temperature range (-40 to 85C) Weight: 0.01 g (typ.)
Product Marking
US8 Type name
Pin Assignment (top view)
CS CLK
DI 6
8
7
DO 5
9WM A2
No.1 pin indicator
1 2 3 4 VCC NC RST GND
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Block Diagram
Chip select CS Clock input
Timing generator
Control circuit
Power supply (booster circuit)
VCC Power supply Reset input RST
CLK
Command register Input/Output circuit Data Output DO Memory cell Address Address register decoder
Data Input DI
GND Ground
Data register
Pin Function
Pin Name Input/Output Input Function Chip select A low on CS selects the chip. Always return CS high temporarily before executing instructions. Clock input The data on DI is latched by a rising edge of CLK . Data is output to DO by a falling edge of CLK . CLK is effective when CS is low. Serial data input This pin is used to enter addresses, commands, and data into the chip. Serial data output This pin outputs data from the chip. Reset input A low on this input resets the chip. No connection (not connected internally) 1.8 V~5.5 V (for reading) 2.3~5.5 V (for writing) 0 V (GND)
CS
CLK
Input
DI DO RST NC VCC GND
Input Output Input
Power supply
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Functional Description
1. Types of Instructions
Operation Read Program All erase Busy monitor Overwrite enable Overwrite disable Read Auto-incremented Address A0~A7 A0~A7
******** ******** ******** ********
Command C0 C1 C2 C3 1 0 0 1 1 1 1 0 1 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Data
D0~D7
A0~A7
*: Don't care
2. Operation Method
Be sure to drive CS and CLK high temporarily before entering an instruction. After CS is asserted low, CLK becomes effective, acting as a serial transfer synchronizing signal. The data on DI is latched on a rising edge of CLK , while data is output to DO on a falling edge of CLK . Instructions can only be executed when the chip is not being programmed or collectively erased (i.e., when the ready/busy status signal is high). However, the Monitor Busy instruction can be entered at any time. Only the commands listed in the above table can be used. Do not use any other command. * Read Entering the Read instruction causes memory data at the specified address to be read out and serially output from the DO pin. * Program Entering the Program instruction causes overwrite operation to automatically start within the chip, overwriting memory data at the specified address with the input data. After the instruction is entered, CS can be driven high even while overwrite operation is still in progress internally. * All Erase Entering the Erase All instruction causes erase operation to automatically start within the chip, erasing memory data at all addresses. After the instruction is entered, CS can be driven high even while erase operation is still in progress internally. This command clears the memory data to 0. * Busy Monitor Entering the Monitor Busy instruction causes a ready/busy status signal to be output from the DO pin. This output signal is low while the chip is being programmed or collectively erased, and is high after programming or collective erase operation is completed. The ready/busy status signal is output continuously until CS is driven high. * Overwrite Enable/Disable Entering the Enable Overwrite instruction places the chip in overwrite enabled mode, where the Program and Erase All instructions can be entered. Entering the Disable Overwrite instruction places the chip in overwrite disabled mode, where the Program and Erase All instructions cannot be entered. Once the chip is placed in overwrite disabled mode, it remains disabled against overwriting until the Enable Overwrite instruction is entered. * Read Auto-incremented After the data at the specified address is output, the subsequent CLK pulse causes the address to be incremented so that the data at the next address is output automatically. After the data at the last address is output, that at the first address will be read and output.
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3. Precautions on Powering Up or Down the Chip
(1) (2) (3) A wait time of 1 ms is required before the chip can start operation after it is powered up. Ensure that RST is low when powering up or down the chip. Resetting the chip places it in overwrite disabled mode.
4. Timing Chart
(1) Read
CS
1 CLK
2
7
8
9
10
11
12
13
14
15
16
17
23
24
DI
A0
A1
A6
A7
1
0
0
0
0
0
0
0
Address
Command
DO
Hi-Z
D0
D6 Data
D7
Hi-Z
(2)
Program
CS
1 CLK
2
7
8
9
10
11
12
13
14
15
16
17
23
24
DI
A0
A1 Address
A6
A7
0
1
1
0
0
0
0
0
D0
D6
D7
Command
DO
Hi-Z
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(3) All Erase
CS
1 CLK
2
7
8
9
10
11
12
13
14
15
16
DI
0
0
1
1
0
0
0
0
Command
DO
Hi-Z
(4)
Busy Monitor
CS
1
CLK
2
7
8
9
10
11
12
13
14
15
16
DI
1
0
1
1
0
0
0
0
Command
DO
Hi-Z
Hi-Z
(5)
Overwrite Enable/Disable
CS
1 CLK
2
7
8
9
10
11
12
13
14
15
16
Enable DI Disable
1
0
0
1
0
0
0
0
Command
1
1
0
1
0
0
0
0
Command
DO
Hi-Z
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(6) Read Auto-incremented
CS
1 CLK
2
7
8
9
10 11 12 13 14 15 16 17
23 24 25
31 32 33
39 40
DI
A0 A1 Address
A6 A7
1
0
0
0
1
0
0
0
Command
DO
Hi-Z
D0
D6 D7 D0 Data A0A7 Address
D6 D7 D0 Data A0A7 + 1 Address
D6 D7 Data A0A7 + 2 Address
Hi-Z
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Absolute Maximum Ratings (Note) (GND = 0 V)
Characteristics Power supply voltage Input voltage Output voltage Power dissipation Soldering temperature (in time) Storage temperature Operating temperature Symbol VCC VIN VOUT PD Tsld Tstg Topr Rating
-0.3~7.0 -0.3~VCC + 0.3 -0.3~VCC + 0.3
Unit V V V mW C C C
200 (25C) 260 (10 s)
-55~125 -40~85
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or even destruction. Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings and the operating ranges. Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook ("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Operating Ranges (Note 1) (GND = 0 V, Topr = -40 to 85C)
Characteristics Supply voltage (for reading) Supply voltage (for writing) Symbol VCC VCC Test Condition Min 1.8 2.3 Max 5.5 5.5 Unit V V
Operating Ranges (Note 1) (VCC = 1.8 to 2.7 V, GND = 0 V, Topr = -40 to 85C)
Characteristics Low level input voltage Symbol VIL 1.8 V < VCC < 2.3 V = Min 0 Max 0.15 x VCC VCC VCC 0.25 2.3 V < VCC < 2.7 V = Min 0 1.6 1.8 0 Max 0.35 VCC V VCC 0.5 MHz Unit V
High level input voltage
VIH1 0.7 x VCC (Note 1) VIH2 0.8 x VCC (Note 2) fCLK 0
Operating frequency
Operating Ranges (Note 1) (VCC = 2.7 to 5.5 V, GND = 0 V, Topr = -40 to 85C)
Characteristics Low level input voltage Symbol VIL VIH1 (Note 2) VIH2 (Note 3) fCLK 2.7 V < VCC < 3.6 V = = Min 0 1.6 2.2 0 Max 0.45 VCC VCC 1 4.5 V < VCC < 5.5 V = = Min 0 2.0 3.0 0 Max 0.7 VCC V VCC 1 MHz Unit V
High level input voltage
Operating frequency
Note 1: The operating ranges must be maintained to ensure the normal operation of the device. Unused inputs must be tied to either VCC or GND. Note 2: Note 3:
CS , DI, RST CLK
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Electrical Characteristics D.C. Characteristics (VCC = 1.8 to 2.7 V, GND = 0 V, Topr = -40 to 85C)
Characteristics Input current Output leakage current Symbol ILI ILO IOH = -1 mA High level output voltage VOH IOH = -500 A IOH = -100 A IOL = 2 mA Low level output voltage VOL IOL = 500 A IOL = 100 A Quiescent supply current Supply current during read Supply current during all erase/program ICC1 (Note 1) ICC2 (Note 2) ICC3 (Note 3) Test Condition 1.8 V < VCC < 2.3 V = Min

2.3 V < VCC < 2.7 V = Min

Max
1 1
Max
1 1
Unit
A A
VCC - 0.4

V
VCC - 0.2

0.4

V
0.2

5 0.5
5 1.0 1.0
A
mA mA
D.C. Characteristics (VCC = 2.7 to 5.5 V, GND = 0 V, Topr = -40 to 85C)
Characteristics Input current Output leakage current Symbol ILI ILO IOH = -1 mA High level output voltage VOH IOH = -500 A IOH = -100 A IOL = 2 mA Low level output voltage VOL IOL = 500 A IOL = 100 A Quiescent supply current Supply current during read Supply current during all erase/program ICC1 (Note 1) ICC2 (Note 2) ICC3 (Note 3) Test Condition 2.7 V < VCC < 3.6 V = Min

4.5 V < VCC < 5.5 V = = Min

Max
1 1
Max
1 1
Unit
A A
VCC - 0.4

VCC - 0.4

V
0.4

0.4

V
5 1.5 1.0
5 2.5 2.0
A
mA mA
Note 1:
CS = 1 (except when busy, however)
Note 2: Current that flows for a period between a fall of the 14th CLK pulse and a rise of the 16th CLK pulse when executing the Read instruction. Note 3: Current that flows while executing the Erase All or Program instruction.
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A.C. Characteristics (VCC = 1.8 to 2.7 V, GND = 0 V, Topr = -40 to 85C)
Characteristics Maximum clock frequency Minimum clock pulse width Minimum reset pulse width Minimum chip select pulse width Reset setup time Symbol fMAX twCLK (L) twCLK (H) tWRST tWCS tRSS tCKS tCSS tpLH tpHL tpZH tpZL (Note) tpLZ tpHZ Input data setup time ts RST setup time when CS is switched over Test Condition 1.8 V < VCC < 2.3 V = Min 0 1.0 1 1 1 Max 0.25

2.3 V < VCC < 2.7 V = Min 0 1.0 1 1 1 Max 0.5

Unit MHz
s s s s
Clock setup time
CLK setup time when CS is switched over
CS setup time when CLK is switched over Time from CLK switchover until valid data is output Time from CS switchover until output data goes Hi-Z Input data setup time when CLK is switched over Input data hold time when CLK is switched over
500
500
ns
CS setup time
500
500
ns
2.0
1.0
s
Propagation delay time
2.0
1.0
500
500
ns
Input data hold time
th
500
500
ns
Note: CL = 100 pF, RL = 1 k
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A.C. Characteristics (VCC = 2.7 to 5.5 V, GND = 0 V, Topr = -40 to 85C)
Characteristics Maximum clock frequency Minimum clock pulse width Minimum reset pulse width Minimum chip select pulse width Reset setup time Symbol fMAX twCLK (L) twCLK (H) tWRST tWCS tRSS tCKS tCSS tpLH tpHL tpZH tpZL tpLZ tpHZ Input data setup time ts RST setup time when CS is switched over Test Condition 2.7 V < VCC < 3.6 V = = Min 0 0.4 1 1 1 Max 1

4.5 V < VCC < 5.5 V = = Min 0 0.4 1 1 1 Max 1

Unit MHz
s s s s
Clock setup time
CLK setup time when CS is switched over
CS setup time when CLK is switched over Time from CLK switchover until valid data is output Time from CS switchover until output data goes Hi-Z Input data setup time when CLK is switched over Input data hold time when CLK is switched over
250
250
ns
CS setup time
250
250
ns
0.25
0.25
s
Propagation delay time (Note)
0.5
0.5
250
250
ns
Input data hold time
th
250
250
ns
Note: CL = 100 pF, RL = 1 k
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< < E PROM Characteristics (GND = 0 V, 2.3 V = VCC = 2.7 V, Topr = -40 to 85C)
Characteristics All erase time Program time Endurance Data retention time Symbol tE tP NEW tRET Test Condition Min

5
2
Typ.
Max 12 12
Unit ms ms Times Year
1 x 10 10

< < E PROM Characteristics (GND = 0 V, 3.0 V = VCC = 5.5 V, Topr = -40 to 85C)
Characteristics All erase time Program time Endurance Data retention time Symbol tE tP NEW tRET Test Condition Min

5
2
Typ.
Max 10 10
Unit ms ms Times Year
1 x 10 10

Capacitance Characteristics (Ta = 25C)
Characteristics Input capacitance Output capacitance Equivalent Internal capacitance Symbol CIN CO CPD fIN = 1 MHz (Note) Test Condition VCC (V) 3.3 3.3 3.3 Typ. 4 3 8.5 Unit pF pF pF
Note: CPD denotes the IC's internal equivalent capacitance calculated from the amount of current it consumes while operating. The average current consumption during non-loaded operation is obtained from the equations below. ICC (Read) = fCLKCPDVCC + ICC1 + ICC23/24 ICC (Prog) = fCLKCPDVCC + ICC1 + ICC3
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A.C. Characteristics Timing Chart
tCKS CS CLK VCC/2 ts CLK DI VCC/2 tPLH tPHL tPLH tPHL VCC GND VCC/2 tPLZ tPHZ CS CLK DO tPZH tPZL VCC/2 HiZ VCC/2 VCC GND VCC GND th VCC/2 VCC GND tCSS VCC/2 tCKS tCSS VCC GND VCC GND
CLK
DO
VCC/2
CLK
DO HiZ
VCC/2 VCC/2
VCC GND
tWCLK (L) tWCLK (H) CLK VCC/2 VCC/2 tWRST RST VCC/2 tRSS RST CS tWCS CS VCC/2 tPZH tPZL CLK DO VCC/2 VCC/2 VCC/2 tPLH tPHL VCC GND VCC/2 VCC/2 VCC GND VCC/2 VCC GND VCC GND
VCC GND
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Input/Output Circuits of Pins
Pin Name CS DI RST Input Type Input/Output Circuit Remarks
CLK
Input
Hysteresis input
Output control signal
VCC
DO
Output
Initial "HiZ"
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Package Dimensions
Weight: 0.01 g (typ.)
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RESTRICTIONS ON PRODUCT USE
* The information contained herein is subject to change without notice.
20070701-EN GENERAL
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.).These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in his document shall be made at the customer's own risk. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.
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